id: Simula.ND.367
ERROR IN ENCODING
title: Flexible DOR Routing for Virtualization of Multicore Chips
publication_year: 2009
abstract: The expected increase in number of cores on a single chip leads to the necessity of high-performance on chip interconnects (NoC). Furthermore, in order to fully utilize the abundance of cores, the chip is expected to support a number of applications running on the chip simultaneously. It is therefore necessary to partition the chip to support numerous applications without any risk of interference between them. The success of this depends on the flexibility of the underlying routing algorithm. This paper presents a flexible routing algorithm based on dimension ordered routing, which supports a large variety of irregular (2-D and 3-D) mesh topologies. The algorithm provides high efficiency at very low additional complexity, as is confirmed by experimental results.
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booktitle: International Symposium on System-on-Chip
editor: Jari Nurmi, Jarmo Takala, Olli Vainio
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publisher: IEEE 
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isbn: 978-1-4244-4465-6
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publication_month: October
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publication_state: Published
simula_ou: [<Department at /simula/department/netsys>]
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category: Conference
from_date: 2009/10/05 00:00:00 GMT+2
to_date: 2009/10/07 00:00:00 GMT+2